Question 1: Semiconductors and Logic Gates

Question

$$ 	ext { The output } Y 	ext { for the given inputs } A 	ext { and } B 	ext { to the circuit is : } $$

Accepted Answer

The inputs are,
Interval I: From $\mathrm{t}=0$ to $\mathrm{t}=1$, Input $\mathrm{A}=0$, Input $\mathrm{B}=1$.
Interval II: From $\mathrm{t}=1$ to $\mathrm{t}=2$, Input $\mathrm{A}=1$, Input $\mathrm{B}=1$.
Interval III: From $\mathrm{t}=2$ to $\mathrm{t}=3$, Input $\mathrm{A}=1$, Input $\mathrm{B}=0$.
Interval
Input A
Input B
I
0
1
II
1
1
III
1
0
For the output $Y_1$ the inputs are $A$ and $B$ directly. The corresponding logic gate is AND gate.
$$ \mathrm{Y}_1=\mathrm{A} \cdot \mathrm{~B} $$
$$ \begin{array}{|l|l|l|l|} \hline 	ext { Interval } & 	ext { Input A } & 	ext { Input B } & 	ext { Output } \mathrm{Y}_1 \ \hline 	ext { I } & 0 & 1 & 0 \cdot 1=0 \ \hline 	ext { II } & 1 & 1 & 1 \cdot 1=1 \ \hline 	ext { III } & 1 & 0 & 1 \cdot 0=0 \ \hline \end{array} $$
For the output $\mathrm{Y}_2$ the input B is directly but input A passes through a NOT gate .
$$ Y_2=\bar{A} \cdot B $$
$$ \begin{array}{|l|l|l|l|l|} \hline 	ext { Interval } & 	ext { Input A } & & \bar{A} & 	ext { Input B } \ \hline 	ext { I } & 0 & 1 & 1 & 	ext { Output } \mathrm{Y}_2 \ \hline 	ext { II } & 1 & 0 & 1 & 0 \cdot 1=0 \ \hline 	ext { III } & 1 & 0 & 0 & 0 \cdot 0=0 \ \hline \end{array} $$
For the final output Y the inputs are $\mathrm{Y}_1$ and $\mathrm{Y}_2$. The corresponding gate is OR gate.
$$ Y=Y_1+Y_2 $$
Interval
Input A
Input B
Y
1
Y
2
Y = Y
1
+ Y
2
I
0
1
0
1
0 + 1 = 1
II
1
1
1
0
1 + 0 = 1
III
1
0
0
0
0 + 0 = 0
Based on the logic analysis of the timing intervals, the correct output graph is represented in option (B).

Answer

Answer

Answer

Answer

Semiconductors and Logic Gates

\text { The output } Y \text { for the given inputs } A \text { and } B \text { to the circuit is : }

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