Question 1: Semiconductors and Logic Gates

Question

$ 	ext{ The output } Y 	ext{ for the given inputs } A 	ext { and } B 	ext { to the circuit is : } $
![](https://app-content.cdn.examgoal.net/fly/@width/image/6y3zli1mnsiw09r/e6ab0794-3423-4203-8527-09b817424a30/31ec6ef0-34a6-11f1-8461-75c223c4ecce/file-6y3zli1mnsiw09s.png?format=png)

Accepted Answer

The inputs are, $\$
Interval I: From $\mathrm{t}=0$ to $\mathrm{t}=1$, Input $\mathrm{A}=0$, Input $\mathrm{B}=1$. $\$
Interval II: From $\mathrm{t}=1$ to $\mathrm{t}=2$, Input $\mathrm{A}=1$, Input $\mathrm{B}=1$. $\$
Interval III: From $\mathrm{t}=2$ to $\mathrm{t}=3$, Input $\mathrm{A}=1$, Input $\mathrm{B}=0$. $\$
$ \begin{array}{|l|l|l|} 
\hline 	ext { Interval } & 	ext { Input A } & 	ext { Input B } \ 
\hline 	ext { I } & 0 & 1 \ 
\hline 	ext { II } & 1 & 1 \ 
\hline 	ext { III } & 1 & 0 \ 
\hline \end{array} $ $\$
For the output $Y_1$ the inputs are $A$ and $B$ directly. The corresponding logic gate is AND gate. $\$
$ \mathrm{Y}_1=\mathrm{A} \cdot \mathrm{~B} $ $\$
$ \begin{array}{|l|l|l|l|} \hline 	ext { Interval } & 	ext { Input A } & 	ext { Input B } & 	ext { Output } \mathrm{Y}_1 \ \hline 	ext { I } & 0 & 1 & 0 \cdot 1=0 \ \hline 	ext { II } & 1 & 1 & 1 \cdot 1=1 \ \hline 	ext { III } & 1 & 0 & 1 \cdot 0=0 \ \hline \end{array} $ $\$
For the output $\mathrm{Y}_2$ the input B is directly but input A passes through a NOT gate. $\$
$ Y_2=\bar{A} \cdot B $ $\$
$ \begin{array}{|l|l|l|l|l|} 
\hline 	ext { Interval } & 	ext { Input A } & \bar{A} & 	ext { Input B } & 	ext { Output } \mathrm{Y}_2\ 
\hline 	ext { I } & 0 & 1 & 1 & 1 \cdot 1=1 \ 
\hline 	ext { II } & 1 & 0 & 1 & 0 \cdot 1=0 \ 
\hline 	ext { III } & 1 & 0 & 0 & 0 \cdot 0=0 \ 
\hline \end{array} $ $\$
For the final output Y the inputs are $\mathrm{Y}_1$ and $\mathrm{Y}_2$. The corresponding gate is OR gate. $\$
$ Y={Y}_1+{Y}_2 $ $\$
$ \begin{array}{|l|l|l|l|l|l|} 
\hline 	ext { Interval } & 	ext { Input A } & 	ext { Input B } & {\mathrm{Y}_1} & \mathrm{Y}_2 & 	ext { Output } \mathrm{Y} \ 
\hline 	ext { I } & 0 & 1 & 0 & 1 & 0 + 1=1 \ 
\hline 	ext { II } & 1 & 1 & 1 & 0 & 1 + 0=1 \ 
\hline 	ext { III } & 1 & 0 & 0 & 0 & 0 + 0=0 \ 
\hline \end{array} $ $\$
Based on the logic analysis of the timing intervals, the correct output graph is represented in option (B).
![](https://app-content.cdn.examgoal.net/fly/@width/image/6y3zli1mo2zlvm6/905510fb-399a-48b0-9c6d-60c6dc76bc2e/69ecdfd0-3a67-11f1-a0ae-9da33830bb19/file-6y3zli1mo2zlvm7.png?format=png', 'https://app-content.cdn.examgoal.net/fly/@width/image/6y3zli1mnsixtv8/2fb4e841-16ab-46ef-90e9-9bc0ec238698/64986340-34a6-11f1-8461-75c223c4ecce/file-6y3zli1mnsixtv9.png?format=png)

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Answer

Semiconductors and Logic Gates

\text{ The output } Y \text{ for the given inputs } A \text{ and } B \text{ to the circuit is : }

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